PHUB priority interrupt usage | Cypress Semiconductor
PHUB priority interrupt usage
Is there any additional documentation available regarding the "pri_int_en" bits of the PHUB_CFG beyond the following paragraph in the register TRM?
"1: Priority can interrupt lower priority channels Bits 22:16 correspond to priorities 6:0. Priority 7
is the lowest priority and thus can not interrupt yet lower priorities and therefore there is no bit for
it." (PSoC 5LP Registers TRM, Document No. 001-82120 Rev. *D, page 1334)
I have failed to spot any mention in the architecture TRM, advanced DMA topics application note or elsewhere.
My reason for asking is that in a scramble to reduce DMA latency I had set these bits and have since experienced peculiar once-in-a-blue-moon races which I believe may be related to their usage but which I have yet to reproduce reliably. In particular I would be interested to know the granularity at which bursts are canceled and resumed, as well as whether reads or writes with side-effects may be duplicated.
For a bit of context I have a low-priority USB transfer continually writing 64-bytes to an endpoint via a burst trigger, for which the interrupt bit set for the priority. What appears to happen, though frankly I am far from certain, is that the interruption occasionally ends up incrementing the DMA source address for the canceled burst.
In this the case the workaround of using shorter bursts of 64-byte transfers has proved reliable thus far but I realized that I haven't quite understood the hardware and so thought I should post a question help bring clarity to my further optimization efforts. Besides, I may simply have altered the timing to mask a race elsewhere.