The mechanics of UART DMA reads from FIFOs...a couple of questions | Cypress Semiconductor
The mechanics of UART DMA reads from FIFOs...a couple of questions
All: perhaps it is my limited cranial capacity, but I am unable to understand exactly how the data is processed into the FIFOs by the UART component and subsequently read out by a DMA.
1) There are two 4 byte FIFOs in each UDB and the UART is (duh) UDB-based. I assume one FIFO is used for the Rx, the other for Tx. Now, do we have a static 4 FIFO elements only for 8 bits, or can they be concatentated/subdivided (2 FIFO elements for 16 bits, etc.)?
2) How do you point the DMA to the correct spot in the FIFO, or is that simply task handled autonomously by the FIFO control logic?
3) What happens if you're trying to read data while the FIFO overruns...it the incoming data simply pre-empted or is the read-out data now corrupted.
4) What is the correct address to use for setting up the DMA. Is the base address PERIPHERAL _BASE? Or should I use UART_($number)_RXDATA_PTR? I assume the upper 16 bits are the UART_RXDATA_PTR.
5) In the UART header file, I notice there is a pointer to the RX_DATA buffer (UART_RXDATA_PTR) and a pointer to a pointer to type reg associated with the buffer (UART_RXDATA_REG). What is the latter used for? Call me dumb by why do you need a pointer to a pointer to the register? Is it used as an argument to some function somewhere?
I tried to find this granularity of data in the TRM documents but thus far I've been unable, so pardon me if any of these questions seem ignorant but I just don't know where to find the detailed information.