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Maximum parallel input speed | Cypress Semiconductor

Maximum parallel input speed

Summary: 1 Reply, Latest post by hli on 04 Apr 2012 03:03 PM PDT
Verified Answers: 0
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Rocketmagnet's picture
131 posts

 If I wanted to clock 8-bit parallel data into the PSoC5 and store it in RAM, what's the theoretical maximum rate I could do that?

Could I clock in bytes at 67MHz?


Many thanks

Hugo Elias



user_78878863's picture
2553 posts

Short answer: Yes and no (or: it depends :).

Long answer: you might want to read the PSoC5 family data sheet and the PSoC5 architecture TRM. Both make no limits to the DMA speed (at least I could not find a direct reference to such a limit). But the application note AN52705 contains an important hint (page 10): the DMA latency can get an issue.

First, the latency affects how fast your transfer starts.

Second, it affects chaining of TDs. You can transfer up to 127 bytes in a single burst, and up to 4095 bytes in a single transfer (if you don't use bursts, all 4095 bytes should get transferred in a row). Anything larger than that will need multiple TDs, and then you have a delay between them.

So the long answer is: until you don't want to transfer more than 4095 bytes, you should be fine with the maximum speed. But anything larger than that will cause problem.

Note that this is solely from skimming through the documentation, so someone more knowledgeable with the PSoC5 might want to correct me :)

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