You are here

Is it optimizing? | Cypress Semiconductor

Is it optimizing?

Summary: 1 Reply, Latest post by srim on 01 Mar 2013 12:30 AM PST
Verified Answers: 0
Last post
Log in to post new comments.
user_228878049's picture
152 posts

 I was driving a clock out of the pin. Basically I am connecting 8 not gates back to back to get a delay from input to output. 

But when I connect the output of clock and output after 8 not gates there is no delsy found. I think the Creator is intelligent enough to optimise the design i guess. How can I generate a delay using gates. Or can I stop Creator optimising the topdesign.

srim's picture
Cypress Employee
111 posts

 Yes, Looks like the creator is optimising out. Not sure if there is way to disable the optimization for the components. Here is a similar post which talked about this kind of problem :

Log in to post new comments.