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How do I synchronize ADC and UDB? | Cypress Semiconductor

How do I synchronize ADC and UDB?

Summary: 8 Replies, Latest post by Piotr Wyderski on 21 May 2017 12:59 AM PDT
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Piotr Wyderski's picture
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33 posts

Hello,

please see the attached project. It is composed of an analog clock, an ADC in external clock mode and a datapath. I would like to run the ADC and the datapath synchronously, which would be simplest if I just use the same clock.

1. The manual says the ADC clock source needs to be one of the 4 analog clocks -- fine.

2. The analog clock can have an additional digital clock output -- OK.

3. I force the clock to be synchronized with MASTER_CLK in the clock's configuration window -- I thought it is enough:

"The clock distribution network produces a master clock, MASTER_CLK, used for resynchronization. This clock is not intended for clocking circuitry outside of the clock distribution network. Output clocks can be phase aligned to this clock. Normally MASTER_CLK should be the highest frequency clock in the chip.

Generally, all clocks used in the chip must be derived from the same source, or synchronized to the main fast clk_sync clock (MASTER_CLK).

By setting this parameter to false this clock becomes an unsynchronized, divided clock."

And now the synthesizer says:

"Error: Routing of asynchrononus signal ClockBlock:clockblockcell.clk_a_dig_0 as a clock to UDB component "\component01_1:path\" is not supported unless a UDB Clock/Enable component is used.

The UDB components other than MacroCells or Sync blocs are designed to be clocked synchronously to BUS_CLK. In special situations clocking these components with an Asynchronous clock may be required and can be supported for specific modes of operation. If the usage of an asynchronous clock has been evaluated as necessary and supportable, then use a UDB Clock/Enable component with the setting for Asynchronous clock operation on the clock signal before sending the clock to the UDB component."

But what exactly is asynchronous here? "The UDB components other than MacroCells or Sync blocs are designed to be clocked synchronously to BUS_CLK."

But since the clock is synchronous to MASTER_CLK, then it by definition is synchronous to BUS_CLK too, as far as I understand the clock routing rules.

Is it a Creator's bug or if not, what exactly should I do in order to make it work?

    Best regards, Piotr

 

 

 

 

 

user_242978793's picture
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1458 posts

The issue is in your model part component01_01. As the compiler was telling you.  You need to change the model to have a a clock enable input.

user_342122993's picture
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790 posts

Pyotr,

When Clock_1 is changed to digital the project compiles without errors. I don't understand project functionality. I see that Datapath is set to 8-bit but ADC produces 2-byte output, would it be a problem? You can also enable "ADC eos" output, and trigger "innn" instantly upon sampling, instead of waiting few microseconds for "ADC eoc" output.    

Piotr Wyderski's picture
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33 posts

Odissey,

the project has no purpose, it is just the minimal testcase to demonstrate the problem, as Bob Marlowe once suggested. What I really want to do is to run datapath in sync with the ADC, namely with its eos/eoc signals in order to avoid clock domain crossing problems. Changing the clock to digital certainly compiles, but, to my understanding, violates the requirements expressed in the manual, 38.2.2: "The clock to the SAR can come from one of the four available analog clocks or a UDB generated clock." IMO a digital clock is neither, if it is legal I wouldn't bother with analog clocks at all.

Bobgoar: the clock enable certainly helps, but ResourceMonitor shows exactly 0 resource usage then, as indicated in its datasheet, BTW, in the case of synced clocks. So is its purpose just a formal notification to indicate the collaborators that analog clock domain crossing happens here, not a technical limitation of any kind?

 

user_342122993's picture
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790 posts

Piotr, I believe that if it compiles without a warning, then it should run ok. Re: to sync ADC and Datapath - ADC is slow device compared to Datapath and operates in its own time domain. If data is being transferred to UDB by DMA, then timing is not guaranteed either, so typically only connection between the above is "eos" signal, which has to pass through Sync component to avoid 'domain crossing' warning.

Piotr Wyderski's picture
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33 posts

Odissey,

it seems that your conviction about the usage of a digital clock is well-grounded. If there are more clocks (whether analog or not), the SAR ADC component code emitter always generates assignment to MX_CLK_0, regardless of the selected clock source. It seems that the routing takes precedence over the register value or the register is totally ignored. But then the documentation is wrong. Which wouldn't be the first time, have a look at the following. PSOC5LP TRM, 38.2.3:

"The user can also retain the earlier DAC value or clear it at the beginning of the new sampling clock. This is done in SARx_CSR0[3] register bit."

which would be extremely strange a feature. The registers TRM, OTOH, page 569, about the said bit:

"SAR_HIZ_RETAIN Higher input impedance mode, caps not reset after conversion"

so it is about the S&H capacitors, not the DAC -- perfectly logical. Even funnier, the opposite setting:

"SAR_HIZ_CLEAR Should not be used"

explicitly marked as "should not be used" is emitted by the ADC_SAR component generator (in the function ADC_SAR_Enable()) with a comment "should not be used on PSOC5LP". :)

 

Piotr Wyderski's picture
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33 posts

It seems I am hitting some length limit, so pt2:

On the contrary, in 38.2.3 TRM says:

"The input sampling time can be programmed from the 1 to 64 cycles in register SARx_CSR2[5:0] register bits."

and in the regs docs of CSR2, page 572:

Value Name Description
0 SAR_SAMPLE_WIDTH_LSB_0 sample time=MSB value*clock period; cannot be used of MSB is 0
1 SAR_SAMPLE_WIDTH_LSB_1 sample time=MSB value + 1 clock cycle

SAR_SAMPLE_WIDTH_MSB_ENUMValue Name Description

0 SAR_SAMPLE_WIDTH_MSB_0 sample time=LSB value * clock period; cannot be used of LSB is 0
1 SAR_SAMPLE_WIDTH_MSB_1 sample time=LSB value + 128 clock cycles
2 SAR_SAMPLE_WIDTH_MSB_2 sample time=LSB value + 256 clock cycles

Look at the meanings of the MSB encodings: 128/256/384 etc. cycles -- there is no way to encode the value of 64... I'll need to verify with a scope which document is wrong here, I assume it is the Register TRM, not the Architecture TRM.

 

Piotr Wyderski's picture
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33 posts

pt3:

But returning to the original problem: eoc is not the only signal in my case, I want to use the datapath to dynamically generate analog routing settings for vplus and vminus, with transitions determined by eos. Since I don't use any analog peripherals except of the ADCs, I decided to use the ResourceReserve component and take AMUXBUSR for vplus and AGR2 for vminus and do the break-before-make GPIO muxing by appropriately programing the BIEs. The DSI signals anded with the BIEs come from a datapath in parallel output mode -- a very resource-efficient solution (1 datapath, 1 macrocell, 1 dynamic mode FIFO for eos edge detection) compared to the AMUXHW component, which ate 1/5 of my resources. That's the reason to do it in sync with the ADC. Ultimately the datapath will also drive the ADC's vn_ctl_udb input, but I don't know what to put there -- the docs remain silent, so I filled a case and wait for a Cypress FAE.

I can show you the project if you are interested, but it is not sufficiently debugged yet (the datapath works correctly, but my ADC has just become operational and I don't know if it measures the inputs correctly).

BTW, why there is no API to change the input sampling time of an ADC SAR component? It seems to be hardcoded to 4 cycles. I would like to have it 6 cycles, which would make exactly 800kSPS on a 16MHz clock. Seems to be another good reason to avoid the high-level wrappers and do things directly with cy_primitives (two other are direct access to the input muxes vp/vn_ctl_udb and the 12-bit parallel output, which can be accessed without DMA in jitter-sensitive applications).

Piotr Wyderski's picture
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33 posts

Odissey,

FYI: the TRM gets the clock selection process right: if you connect a digital clock to aclk/pump_clk of the cy_primitive SAR ADC, the component compiles without a warning, but doesn't start due to the lack of clock when MX0..MX3 sources are used. The clock must be analog for that settings.  In order to make it work as I want, one needs to connect the desired digital clock to the clock_udb terminal and then select MX4 for both aclk and pump_clock in the CLK register.

I thought that the results of my experiments might be useful for somebody in the future, so I decided to share this knowledge here.

    Piotr

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