How do I synchronize ADC and UDB? | Cypress Semiconductor
How do I synchronize ADC and UDB?
please see the attached project. It is composed of an analog clock, an ADC in external clock mode and a datapath. I would like to run the ADC and the datapath synchronously, which would be simplest if I just use the same clock.
1. The manual says the ADC clock source needs to be one of the 4 analog clocks -- fine.
2. The analog clock can have an additional digital clock output -- OK.
3. I force the clock to be synchronized with MASTER_CLK in the clock's configuration window -- I thought it is enough:
"The clock distribution network produces a master clock, MASTER_CLK, used for resynchronization. This clock is not intended for clocking circuitry outside of the clock distribution network. Output clocks can be phase aligned to this clock. Normally MASTER_CLK should be the highest frequency clock in the chip.
Generally, all clocks used in the chip must be derived from the same source, or synchronized to the main fast clk_sync clock (MASTER_CLK).
By setting this parameter to false this clock becomes an unsynchronized, divided clock."
And now the synthesizer says:
"Error: Routing of asynchrononus signal ClockBlock:clockblockcell.clk_a_dig_0 as a clock to UDB component "\component01_1:path\" is not supported unless a UDB Clock/Enable component is used.
The UDB components other than MacroCells or Sync blocs are designed to be clocked synchronously to BUS_CLK. In special situations clocking these components with an Asynchronous clock may be required and can be supported for specific modes of operation. If the usage of an asynchronous clock has been evaluated as necessary and supportable, then use a UDB Clock/Enable component with the setting for Asynchronous clock operation on the clock signal before sending the clock to the UDB component."
But what exactly is asynchronous here? "The UDB components other than MacroCells or Sync blocs are designed to be clocked synchronously to BUS_CLK."
But since the clock is synchronous to MASTER_CLK, then it by definition is synchronous to BUS_CLK too, as far as I understand the clock routing rules.
Is it a Creator's bug or if not, what exactly should I do in order to make it work?
Best regards, Piotr