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Datapath FIFO in Single Buffer Mode and AUX control registers. | Cypress Semiconductor

Datapath FIFO in Single Buffer Mode and AUX control registers.

Summary: 0 Replies, Latest post by rahulram on 07 Mar 2013 02:56 AM PST
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rahulram's picture
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 The data path FIFOs in the PSoC3/5 UDB can be used as a single buffer; rather than a FIFO of depth 4. In this case, what happens is that, the FIFO read and the write pointers does not increment/decrement and will create an apparent illusion that only a single register exist. 

When the FIFO is used as a single buffer, we shall not worry about the status signals. We can read and write data from and in to the FIFOs at our will. We should also be cautious about the fact that FIFO can be overwritten and hence will require a proper read signal (which should all be taken care, inside the verilog code) before the next data could be written.

To configure the FIFO in a single buffer mode, we need to set the lower 2 bits in the Auxillary control register. It is advised that when ever we modify the auxillary control registers, we should do it with the interrupts disabled. Hence, we can do this change inside the critical region. The procedure to enter the critical region and modify the auxillary control register is given below.

AUX Control Register :

7 6 5 4 3 2 1 0
NA NA Counter Start Interrupt Enable FIFO 1 LVL



Counter Start - This will start the inbuilt 7 bit counter.

Interrupt enable-- The status register shall sometimes be used to generate interrupts. for ex, we can generate an interrupt on every FIFO load, so that the CPU can read the contents. This can be done by using the status register and by setting the bit4 of the AUX CTL register.

 FIFO 1 and 0 LVL bit setting will enable the half or full bus status. By default the value is 0 and when the LVL is 0, the two issued bus signals are "Not empty" and "half full"  for the output configured FIFO; while it will be " Not Full" and "Half empty" for an input configured FIFO. Whne the LVL is set to 1, the 2 BUS signals will change from half full and half empty to "full" and "empty".

This means that the FIFO status signals will be for a depth of 4 rather than 2.

The CLR register bits, when set, will make sure that the FIFO is used in the single buffer mode and there is no dependancy on the status signals.


To enter the critical region and modify the contents of the registers, follow the procedure shown below in the code.


#define MYCOUNT7_AUX_CTL (* (reg8 *) MyInstance__CONTROL_AUX_CTL_REG)

uint8 interruptState;

/* Enter critical section */

interruptState = CyEnterCriticalSection();

/* Set the Count Start bit */

MYCOUNT7_AUX_CTL |= (0x03);

/* Exit critical section */





Happy Designing,

Rahul ram

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