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​CY8CKIT-050 PSoC® 5LP Development Kit | Cypress Semiconductor

​CY8CKIT-050 PSoC® 5LP Development Kit

Summary: 15 Replies, Latest post by hli on 24 Oct 2016 05:17 AM PDT
Verified Answers: 3
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muhammad.yaqoob_1490236's picture
User
53 posts

Dear All,

​CY8CKIT-050 PSoC® 5LP Development Kit is based on CY8C5868---(67 MHz). Is there any other development kit which is based on CY8C5888---(80MHz)? (except CY8CKIT-059).

HIMA's picture
Cypress Employee
205 posts

Hello,

Third party kits with PSoC5LP chip are available. Please have a look at link:https://www.sparkfun.com/products/13229

Thanks,

Hima

muhammad.yaqoob_1490236's picture
User
53 posts

Thanks. Actually, they are in the lack of LCD and POT and many other useful resources. 

michal.reznicek_1607246's picture
User
17 posts

Hello can you help me someone? 

 

I have PSOC 5 LP and I would like try SPIM comunication. I used the SPIM block and I sent clock to the 1MHZ and 11bit word. After that I conected the logic probe to the pins on kit (without peripheral) and I sent 0b10101010101 mesage. The problem  is in peaks on CS (SS) and RX and TX (the probe 3 is CS and probe 2 is clock and 0-MOSI and 1 - MISO)

 

Can you help me someone where can be problem? 

 

 

/* ========================================
 *
 * Copyright YOUR COMPANY, THE YEAR
 * All Rights Reserved
 * UNPUBLISHED, LICENSED SOFTWARE.
 *
 * CONFIDENTIAL AND PROPRIETARY INFORMATION
 * WHICH IS THE PROPERTY OF your company.
 *
 * ========================================
*/
#include <project.h>

uint8 pocVzSawtooth = 250;
uint16 delickaOutSawtooth = 0; // inicializace delicky kmitoctu pro výstupní sawtooth
uint32 fOsc = 77000000;
uint16 fsin = 6700; // frekvence pily Hz
uint8 temp = 0;

void nastavGenPily(uint16 fSin);

int main()
{
    CyGlobalIntEnable; /* Enable global interrupts. */

    /* Place your initialization/startup code here (e.g. MyInst_Start()) */
    Opamp_Start();
    WaveDAC_Start();
    SPIM_1_Start();
    for(;;)
    {
        /* Clear the transmit buffer before next reading (good practice) */
        SPIM_1_ClearTxBuffer();

        temp = SPIM_1_ReadTxStatus();

        /* Ensure that previous SPI read is done, or SPI is idle before sending data */
        if(temp & (SPIM_1_STS_SPI_DONE | SPIM_1_STS_SPI_IDLE))
        {
            SPIM_1_WriteTxData(0b10101010101);
            CyDelay(1);
        }
    }
}

/* [] END OF FILE */
void nastavGenPily(uint16 fSin)
{
    // Nastaveni generatoru sinusovky a bileho sumu
    delickaOutSawtooth = fOsc / (fSin*pocVzSawtooth); // vypocet honoty delicky pro generovani sin prubehu o frekvenci fSin [Hz]
    Clock_sawtooth_SetDividerValue(delickaOutSawtooth);// nastaveni hodin pro generator sinusovky
}

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user_1377889's picture
User
9606 posts

A pitfall is the select line, which is automatically taken low when a byte is sent. When the buffer is empty it is taken high again. This can lead to interface errors when the byte sequence is not provided fast enough resulting in ss-line glitches.

A way out is to control an own ss line: before a complete transaction starts, set the line low, when finished return to high again. Use the Pin_Write() API for that.

Bob

 

michal.reznicek_1607246's picture
User
17 posts

Helo BOB,

 

thank you very very much !!! Perfect it is working well now!

user_1377889's picture
User
9606 posts

Great! You are always welcome, Michal.

 

Bob

michal.reznicek_1607246's picture
User
17 posts

:D but when i connect AD5206 digital potenciometer so It doesn't work. I think that the problem is in timing the falding edge on SS because delay betven SS falding edge and clock (CLK) is not carry when i use handcontrol SS using:

        ss_1_Write(0);
        SPI_WriteTxData(data);
        while(!(SPI_ReadTxStatus() & SPI_STS_SPI_DONE));
        ss_1_Write(1);

Do you have some idea?

 

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hli
user_78878863's picture
User
2582 posts

According to your data sheet, there is no required maximum time between the falling flank on SS and the start of transmission. The only requirement is that CLK is low when idle (and this needs to be configured correctly).

(Actually SPI has no maximum timing requirements on the sending side, since it relies on SS and CLK flanks only. It just needs some minimum setup times).

user_1377889's picture
User
9606 posts

Difficult to guess, please provide a workspace bundle.

 

Bob

michal.reznicek_1607246's picture
User
17 posts

Ok, thank you .... It is my small school project ;) .... 

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