Combinational Loop | Cypress Semiconductor
during the design process PSoC produced a warning that I created a combinational loop. After searching for this term I understand what it is but not why it is a problem.
I uploaded a project for the specific problem. There are two inputs (resistive pull-down) und two outputs. If one of the inputs goes high, the corresponding output should go high as well, if the other input is low. If one input and therefor one output is high and the second input goes high as well, the output should stay the same.
To break the loop you could add a D-FlipFlop into the loop but I don't understand why this should improve the behavior?
Are there any problems that could occure I currently don't think about?