You are here

Combinational Loop | Cypress Semiconductor

Combinational Loop

Summary: 2 Replies, Latest post by danaaknight on 04 Aug 2015 08:43 AM PDT
Verified Answers: 1
Last post
Log in to post new comments.
Dominik Gebhardt's picture
12 posts


during the design process PSoC produced a warning that I created a combinational loop. After searching for this term I understand what it is but not why it is a problem.

I uploaded a project for the specific problem. There are two inputs (resistive pull-down) und two outputs. If one of the inputs goes high, the corresponding output should go high as well, if the other input is low. If one input and therefor one output is high and the second input goes high as well, the output should stay the same.

To break the loop you could add a D-FlipFlop into the loop but I don't understand why this should improve the behavior?

Are there any problems that could occure I currently don't think about?


Best regards.

user_1377889's picture
9301 posts

When you set up a truth table for your in- and outputs you may see that there are some indeterministic states which could lead to oscillation.

An analys of your equation delivers that there are no oscillating states:

Q = (A & !B) | (A & Q)

A    B    Qn   Qn+1
0    0    0    0
0    1    0    0
1    0    0    1*
1    1    0    0
0    0    1    0*
0    1    1    0*
1    0    1    1
1    1    1    1

* indicates change in output Qn+1

Each state with an output change leads to a state with the same output value, so it is stable.




user_14586677's picture
7646 posts

I see the feedback condition, odd though does not look latching because of the AND.


Try a clocked LUT, that would force it to be registered and sampled.


Regards, Dana.



Log in to post new comments.