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In - circuit testing and boundary scan | Cypress Semiconductor

In - circuit testing and boundary scan

Summary: 3 Replies, Latest post by danaaknight on 21 Aug 2012 03:39 PM PDT
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user_228878049's picture
152 posts

Hello All

May i know how is in- circuit testing performed.....

What is "bed of Nails"......How is the test performed with bed of nails?

Boundary scan is done with the scan cells within the chip. So if i connect the chip to in - circuit tester(bed of nails) and perform boundary scan is there a possibility that the chip will fail in boundary scan??


user_228878049's picture
152 posts

And secondly . . in the boundary scan when do you say that the test has failed..please provide some examples...

user_1377889's picture
9245 posts


Boundary scan and chip testing or PCB-testing (with a bed of nails) is nothing special to PSoC. Better ask Mrs. google for more infos or find something in wikipedia.



user_14586677's picture
7646 posts

A tutorial -


Bed of Nails refers to a grid array of spring loaded pins, where pins are

loaded into specific geometrical coordinates corresponding to test pads

on a PCB. The PCB has alignment holes, usually at corners, to facilitate

accurate registration of the pins. Thats how a tester gains connection to a

PCB. Then a test program issues various stimulus, V & I, and measurements

are made. Think of a system level test.


Boundary scan plays a role both in chip testing and board level testing, the tutorial

will cover that.


Teradyne key supplier in test equipment. Maybe they have some training videos

that will give you an overview.


Regards, Dana.

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