CapSense theory question | Cypress Semiconductor
CapSense theory question
I have already read "Getting started with CapSense" and the "PSoC3 and PSoC5LP CapSense Design Guide" but I still have a question regarding how CapSense works. In the design guide you will find figure 2-3 CapSense CSD Block Diagramm. For example I start scanning whether Button1 is pressed or not. CMOD is charged via SW3 and the source current. If the voltage equals a reference, the sigma delta converter opens SW3. The converter counts the ticks, how long SW3 is closed. From the amount of ticks you can say if the button is pressed or not.
What I don't understand is SW2 and SW1. I started the scanning and SW3 is open since CMOD is charged. Then SW1 and SW2 are opening and closing alternatively. Lets say the button is pressed and SW1 is closed and so SW2 is open. Cx is discharging CMOD depending on the capacitance of Cx. Then SW1 and SW2 change states so Cx is being discharged. And this will repeat several times.
Is CMOD charged completely again in one cycle, so if SW1 closes again, SW3 will be open or can it happen, that when SW1 is closed, SW3 is closed as well?