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ADC input selection through UDB | Cypress Semiconductor

ADC input selection through UDB

Summary: 2 Replies, Latest post by Piotr Wyderski on 23 May 2017 01:11 PM PDT
Verified Answers: 0
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Piotr Wyderski's picture
28 posts

The manual says that the input sources of a SAR ADC can be set via registers or via the dedicated hardware signals. I can barely find the meaning of the register settings in the documentation (e.g. in SAR1_SW1 there is vp_ag7 Connect positive voltage input to analog global of same side), but how does it work in the case of UDB?

In SAR1_CSR1 there is swvp_src SAR positive input routing control source:

Value Name Description
1'b0 SAR_SWVP_SRC_REG ANAIF SAR routing registers

Say I set it to SAR_SWVP_SRC_UDB. Then the cy_primitive SAR provides a 4-bit vp_ctl_udb input port and also a 4-bit vn_ctl_udb. But what is the meaning of the values encoded there? Let's say I want to connect vminus to VSSA by specifying a 4-bit value generated by UDB. What should the value be and how do you know it? I see nothing about it in the documentation.

Ramesh B's picture
Cypress Employee
41 posts

The input of the SAR ADC is from analog components through the analog routing or from GPIO.

The UDB output cannot be connected as analog input. In SAR1_CR1, swvp_src mentions the control source of the SAR through the ANAIF SAR routing control register or through the UDB. This control sources are SOC, sampling clock or SAR Mux selection signal but not the analog input for the SAR block. I am sorry that the complete information is not given in documentation.

To connect SAR negative input to VSSA, kindly use the SAR0_SW3 for SAR0 block. The more information about the register is provided in the below link, page no 676:

Let me know if this helps. 

Piotr Wyderski's picture
28 posts

No, Ramesh, I'm afraid it does not help at all. You just copied your answer from the support case and, as I already told you there, it is not an answer to my question. So here is my copy-paste:

I have never wanted, let alone asked, about connecting the UDB output as an analog input. The result of such a measurement would obviously be meaningless. I want to control ADC input selection using UDB. Have a look at the PSOC5LP TRM, page 398. Input selection, 38.2.1:

The input selection, both positive and negative, is made through the input selection mux, which can be controlled through either the SAR routing registers in the analog interface or through the UDB. Setting the SARx_CSR[4] bit takes the positive input through UDB and clearing the bit takes the positive input through registers. Similarly, setting the SARx_CSR[3] bit takes the negative input through UDB and clearing the bit takes the negative input through registers.

So, as you can see, the UDB can control the input MUX somehow, at least according to the manual. I presume the vp_ctl_udb and vn_ctl_udb buses of the primitive component are then carrying the MUX selector values. The problem is that these values are not documented and this case is all about that. Please provide me with the encodings, I don't want to guess them blindly.

vn_ctl_udb = 4'b0000 means?

vn_ctl_udb = 4'b0001 means?

vp_ctl_udb = 4'b0000 means? etc.

What you describe later in your text it how to configure inputs via the ANAIF registers. This is well documented, but this is not my case.

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