ADC Clock and EoS | Cypress Semiconductor
ADC Clock and EoS
I had been reading SAR ADC documentation, now i had read the PSoC 5LP Architecture TRM Rev *C, page 388, 38.2.3 Input Sampling section, it says the input sampling time can be programmed from 1 to 64 cycles in register SARx_CSR2[5:0] register bits, so i make a simple project where the ADC is configured to 8bit resolution, continuous sampling, i enable the EoS output and attach a digital output to it, also another to the EoC output and another one to the external clock that is feeding the ADC (1MHz clock), then i debug the component and SARx_CSR2 = 0x0440, this means the sampling time is 4 clock cycles and 8bit resolution.
Later after the same section says: "The conversion time is 18 cycles for input sampling time up to four cycles.", but i see only 14 clock cycles when i plug a logic analyzer to the output, attached are two images that almost explain this. The project just configures the ADC.
Any idea on why i see 14 instead of 18 clock cycles? the logic analyzer trigger is tricking me again?
Thanks in advance