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Access 8-bit FIFO data from verilog | Cypress Semiconductor

Access 8-bit FIFO data from verilog

Summary: 3 Replies, Latest post by PSoC73 on 17 Oct 2013 12:15 AM PDT
Verified Answers: 0
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mmcmaster's picture
2 posts

Is it possible to access the contents of the A0 register within Verilog ?

There are plenty of examples of using verilog to send the output of the Datapath shifters to a pin.  But I cannot find any example of sending an 8-bit parallel value from the FIFO to an output pin via the datapath.

Eg. Load a value from the FIFO into A0, have the ALU perform an operation on it, then have verilog access the result to direct it to an output pin.

The various datapath documention shows the 8-bit PO (parallel output) signal being connected to the input of SRCA. But there is no documentation how to make use of this output!


mmcmaster's picture
2 posts

I found some clues on using PO and PI from another forum post at:

Looks like I need to transition from the cy_psoc3_dp8 module to the base cy_psoc3_dp module to get access to them.


user_119377051's picture
866 posts

Hello mmcmaster

Please look at this article, 13/Oct P5LP_DDS[2].() file

It is use Control register and Status register for passing 8bit data to Verilog module.

Look component TAB, DDS.cysch file,

DDsCore is the Veriog module.

It's not use data_path however,

This handy way is doable what you want to.

Can it help you?

user_14586677's picture
7646 posts

I will let an expert answer this, but this might be useful -     AN82156


Regards, Dana.

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