UART Clock Warning | Cypress Semiconductor
UART Clock Warning
I've included the standard UART block in my project and configured it with baud rate 115200, external interrupt, RX FIFO not empty.
I'm getting the following warning. I don't get the warning if I reduce the baud rate to the one lower. But we need the 115200 for our project. Can you please help me to get rid of this warning?
Clock Warning: (WiFi_Host_SCBCLK's accuracy range '1.333 MHz +/- 2%, (1.307 MHz - 1.36 MHz)' is not within the specified tolerance range '1.382 MHz +/- 5%, (1.313 MHz - 1.452 MHz)'.).
Thanks & Regards,