Tristate data bus drive best approach? | Cypress Semiconductor
Tristate data bus drive best approach?
I'm looking at using a PSoC MCU (current candidate is CYBLE-214009), to add modern connectivity and capabilities to a vintage hand-held computer.
To interface, I'm attempting to make the MCU emulate RAM/ROM (original RAM has 200ns access time), and read/write data, instructions, and status into/out of it over a range of addresses.
I think I'll be able to read the address bus with a status register and using an external pair of bus switchers to read the 16 bits in two 8-bit reads.
For the 8-bit data bus, I need a tristate interface so I can read or drive the data bus, depending on the value of the R/W signal from the handheld. It looks like older PSoC devices supported an EMIF device that would have been a ready-made solution for this, but, for some reason, this is not supported for PSoC 5.
What am currently thinking are 8-bit control and status registers, connected together through a bufoe per bit, and then to a bidirectional pin per bit. The bufoes will have their OEs connected together and to the R/W signal from its input pin.
First of all, will this work? Are there any special configuration settings required in the registers or in the bidirectional pins to make all this act like tristate?
Secondly, is there a way to make hooking these devices together easier and cleaner? Already with just one bit connected it looks pretty messy on the TopDesign view.
After reading through the Using GPIO pins document, I'm wondering whether I actually need the bufoes. It seems like I should be able to hook both registers directly to the I/O pins, and set their behavior through the BIE registers (1 = OE, 0 = Hi-Z). Is that correct?
I tried a couple of tests:
First one with a Bufoe, a bidirectional pin, and three registers (one to set OE of the Bufoe, one for Control output, and one for Status input). This worked fine to alternate between driving a strong drive output and reading a strong drive input. I guess there's some magic that hooks the Bufoe OE to the drive mode of the bidirectional pin.
Second was without the Bufoe and just connecting both of the registers to the bidirectional pin. In this case, I was trying to directly set the drive mode of the pin at runtime (Hi-Z to read, and Strong to write). However, this code fails to program due to "Multiple drivers" on the line connecting the bidirectional pin to the two registers.
So, at this point, the setup with a bank of Bufoes seems like the better bet. Code-wise it will probably be easier, though it will certainly be messier on the layout. Any other thoughts? Is there some reasonable way I can define my own component with 1 to n bits of Staus register, Control register, and Bufoe?