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Reconfigure UART RX pin to GPIO after 10sec | Cypress Semiconductor

Reconfigure UART RX pin to GPIO after 10sec

Summary: 1 Reply, Latest post by GYAN on 20 Jul 2017 05:06 AM PDT
Verified Answers: 0
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user_345714255's picture
User
9 posts

I need to reconfigure the PSOC4-BLE (CYBLE-214009 module) SCB UART RX pin on P14 from the UART to a generic GPIO.

I have followed several threads but they're all reconfiguring the GPIOs in slightly different ways and I can't see how to do what I want.

I have figured out I need to write some of the HSIOM registers and their definitions are in cyfitter.h.

/* UART_rx */
#define UART_rx__0__DR CYREG_GPIO_PRT1_DR
#define UART_rx__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define UART_rx__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define UART_rx__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define UART_rx__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define UART_rx__0__HSIOM_GPIO 0u
#define UART_rx__0__HSIOM_I2C 14u
#define UART_rx__0__HSIOM_I2C_SDA 14u
#define UART_rx__0__HSIOM_MASK 0x000F0000u
#define UART_rx__0__HSIOM_SHIFT 16u
#define UART_rx__0__HSIOM_SPI 15u
#define UART_rx__0__HSIOM_SPI_MOSI 15u
#define UART_rx__0__HSIOM_UART 9u
#define UART_rx__0__HSIOM_UART_RX 9u

...

#define UART_rx__PC CYREG_GPIO_PRT1_PC
#define UART_rx__PC2 CYREG_GPIO_PRT1_PC2
#define UART_rx__PORT 1u
#define UART_rx__PS CYREG_GPIO_PRT1_PS
#define UART_rx__SHIFT 4u

But which register do I need to write and what value do I need to set the GPIO back to using the DR regs for the output level?

gyan's picture
Cypress Employee
19 posts

Hi,

     Each port x has an associated HSIOM_PORT_SELx register to multiplex  the pin and connect to a particular peripheral selected by the user. Value 0 configure the pin to be regular firmware-controlled I/O.

Suppose SCB UART Rx and Tx are routed to P1.4 and P1.5 respectively. Then, write 0 to the bits of HSIOM_PORT_SEL1 register corresponding to pins 4 and 5. Later you can set the drive mode to strong drive depending on application. Please find appended code snippet for reference.

    CY_SET_REG32(CYREG_HSIOM_PORT_SEL1,CY_GET_REG32(CYREG_HSIOM_PORT_SEL1) & 0xFF00FFFF);

    UART_rx_SetDriveMode(UART_rx_DM_STRONG);

    UART_tx_SetDriveMode(UART_tx_DM_STRONG);

 

Regards,

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