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PSoC Creator miswire? OP1 neg to VDD, Dig Drive Ena to VDD? | Cypress Semiconductor

PSoC Creator miswire? OP1 neg to VDD, Dig Drive Ena to VDD?

Summary: 1 Reply, Latest post by bobgoar on 26 Sep 2016 08:58 PM PDT
Verified Answers: 0
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grrasic_1882326's picture
1 post

I'm new to the Cypress Environment and am using the CY8CKIT-042-BLE Pioneer Kit and PSoC Creator 3.3 to develop an application. I have seen where a digital output pin which was supposed to be enabled by a PWM output was instead always enabled as though the ENA pin was tied hi. By switching the pin the problem was corrected. I'm now being stumped as to why an Analog pin set to Hi impedance and tied directly to the negative input of the first Op amp has a lo impedance connection to 4.22V on the Kit board (assigned by the tool to P1-4, pin 32). I have included a N_1_SetDriveMode(N_1_DM_ALG_HIZ) instruction in the code for the pad with no change. Could someone give me some new things to check that may be causing this? Also, I have wired together (in the TopDesign tab) the positive inputs of both opamps together to an analog hi-z pad and to the unused analog mux inputs for channel 1-3 along with the negative input for channel 0. I set the ADC_SAR_12Bit to use internal 1.024V VREF, bypassed and to sample differentially. The analog wiring diagram reflects the circuit I entered properly. However, the pin has 2.54V appearing on it rather than the 1.024V I expected. Is there something fundamentally wrong with this configuration? Thank you, Richard

user_242978793's picture
966 posts

Please post your code so we can check this out.


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