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PSoC BLE + UDB / PLD utilization AN91162 | Cypress Semiconductor

PSoC BLE + UDB / PLD utilization AN91162

Summary: 2 Replies, Latest post by labz.myr on 21 Jan 2016 07:06 PM PST
Verified Answers: 1
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labz.myr's picture
3 posts


Does BLE instance uses PLD / UDB part of device?
I am using PSOC4 BLE module from CY8KIT-042-BLE. 
  • When compiled and configured  AN91162 e'thing worked.
There's no mention of PLD resource utilization. Resource Meter says : Pre-Configured Blocks : 0.0%
  • Instead of PrISM, want to have my own functionality. That functionality being timing critical has been written in verilog and a custom component is created. 
This custom component works as desired when configured stand-alone  on PSOC4  BLE (I could see signals  toggling on oscilloscope
It's utilization is: 
PLD Packing Summary
            Resource Type : Used : Free :  Max :  % Used
                     PLDs :    4 :    4 :    8 :  50.00%
  • Later, I combined 2 cases mentioned above.
    • So that I can control my custom component through same scheme instead of PrISM and the LEDs.
  • But now, the PLD resource utilization has jumped to 225% 
  • Error: mpr.M0014: Resource limit: Maximum number of Pre-configured Blocks exceeded (max=4, needed=9). (App=cydsfit)


Why is it so ? 
Any possible solution ? Is CY8C4247 variant available with higher density PLD ?
user_78878863's picture
2551 posts

This sounds like a question for Cypress. So maybe create support case ('MyCases' in the top right menu), attach the project and ask them. It would be nice if you tell us the answer afterwards :)

labz.myr's picture
3 posts

The problem was at my end.  Cypress guys correctly pointed-out in the support case.

The "custom component" when I had tried stand-alone : Few primary inputs were hard-coded to 1 / 0 etc. That lead Cypress synthesis tool to optimize my RTL and made it "fit" in available  PLD / UDB .

In integration time with BLE,  these inputs are to be driven by Control Register which is written by data received over BLE. This time, Cypress synthesis tool (obviously) doesn't  optimize my RTL and exceeds the available PLD / UDB ! 





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