Problem with interrupts and output pins... | Cypress Semiconductor
Problem with interrupts and output pins...
I'm still stuck on a couple of things with my project. This is a project to add SD storage and BLE communications to a 1982 pocket computer. I'm trying to interface the PSoC to LH5801 CPU by emulating RAM. I am able to write data from the MCU to the CPU, but things are breaking down when I try to read the data bus and use the R/W signal.
Right now, I have a decoded CS on P0.5. This has an interrupt on falling edge that triggers the main routine to read the address bus and see what needs to be done. The R/W line goes to P0.4, and is also ANDed with the inverted CS signal to control OE of the data bus pins.
Looking at the timing diagrams for the PC, it seems that R/W pulses low after address and data are set up when writing to memory. So, I would like to have an interrupt on R/W that gets enabled when CS goes low, and disabled when CS goes high. The W interrupt handler would then read the data bus and write the data to MCU memory.
The problem I'm stuck on is that I can't find how to enable interrupts for both P0.4 and P0.5, and, when I tried to move R/W to one of the remaining available pins (P4.0-1, or P5.0-1) the designer tells me that the function is not reachable from those pins. I can't use anything on P1, P2, or P3, because those ports are fully allocated for address and data lines.
I thought there was a way to have more than one interrupt per port. Can someone tell me more about this, or how I can use P4 or P5?