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CYBLE-214009-00: I/O routing and SPI throughput issues. | Cypress Semiconductor

CYBLE-214009-00: I/O routing and SPI throughput issues.

Summary: 10 Replies, Latest post by IrY100Fan on 01 Nov 2016 07:16 AM PDT
Verified Answers: 2
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IrY100Fan's picture
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5 posts

Hi Everyone,

I am having multiple issues implementing a project on the CYBLE-214009-00 module.  I had my project up and running on the BLE Pioneer Kit using the PSoC 4200BLE board.  But when I went to transfer the project to the CYBLE-214009-00 module, I ran into numerous problems.  As a last resort before asking the gurus here to help me, I tried setting up a blank project and implemented only the external I/O in an attempt to see if I have some goofy code or file corruption in my project.  Unfortunately, I get the same results with a new blank project.

Here are three issues I have run into so far. (More may be lurking behind these...)

  1. Can't assign "\CapSense: CMod" to P4.0.
    According to the CYBLE214009-00 module datasheet, it looks as if there is a "CMod" cap inside of the BLE module connected to P4.0.  The pin P4.0 is shown in the drop down box of the pin assignment editor, but it has a gray box next to it.  If I select it, I receive the message "Pin Error: (Invalid pin assignment P4[0]. This pin does not support ANALOG.)".  (This is a very interesting result as the datasheet says "Any GPIO pin can be CapSense, LCD, analog, or digital".)
     
  2. Can't set the SPI and I2C data rates to maximum.
    When I had originally prototyped this project on the BLE Pioneer Kit, I was able to set the SPI to it's maximum throughput of 8Mbps by manually setting the Oversampling option to "6".  However, on the CYBLE-214009-00 module, it tells me the throughput will be 4.785Mbps...that's kind of a far cry from 8.  I am not sure why this works differently on this module vs the Pioneer board.  Also, I get a similar issue with the I2C, but that speed is close enough to be tolerable.  (Assigned speed 400kpbs, calculated 380kbps.  Although I got 400kbps on the Pioneer board.)
     
  3. Can't disable the SPI Slave Select functionality.
    The SPI devices I am using are kind of goofy.  They require the Slave Select lines to be held sometimes and cycled others.  I accomplished this on the Pioneer board by setting the "Number of SS" option to "0" and controlling the lines with software GPIO.  On the BLE module I can't disable the SPI's automatic Slave Select option, nor can I change how may slave selects I can assign.  Again, this is not an issue on the Pioneer board.

I apologize if I'm just being dumb and missing the obvious.  I am new to the PSoC components and this is my first complete project using these components.  Any assistance will be greatly appreciated.

Thanks.
-Brian

user_242978793's picture
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1029 posts

Post your code please.

user_1377889's picture
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9572 posts

Welcome in  the forum, Brian.

As my name twin suggested, post your complete project, so that we all can have a look at all of your settings. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.

 

Bob

IrY100Fan's picture
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5 posts

Hi Bob and Bob,

I managed to resolve the SPI problems...
I originally had created a new project under an existing workspace and had issues.  I created a new workspace and then a new project and the SPI / I2C issues disappeared.  (I have had other issues with one project interfering with another in the same workspace.  It seems the "Safe Bet" is to create a new workspace for each project.)

On with the CapSense issue...
I am still having an issue assigning the CapSense CMod signal to the CMod pin ( P4[0] ) in the CYBLE214009-00 module.  Attached is new project I created with only a CapSense module and nothing else.  (I created this new project to eliminate any possibility of some other component interfering with pin placement.)

Attached is the new empty project I am using to figure out the CMod issue.

Thanks for the assistance.
-Brian

user_1377889's picture
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9572 posts

I cannot see that the CYBLE214009-00 even has got a port4. I will inform Cypress about that issue. I do not think that the module already has a cap for cmod.

 

Bob

IrY100Fan's picture
User
5 posts

According to the datasheet for the CYBLE214009-00 module, on page 13 it shows that there is a CMod capacitor (2.2nF) connected between Gnd and P4.0 internally in the module.  Also, in the pin assignment editor, P4.0 is marked as having CMod functionality.  My assumption is I should be able to assign the CMod signal to P4.0.  (But I have been wrong many, many time before.)

-Brian

 

user_242978793's picture
User
1029 posts

You can't assign CMod to P4.0 as it is not assessable. See this chart. I assigned the CapSense to another pins and it was ok with the program.  

jrow's picture
Cypress Employee
37 posts

Brian is correct in this case concerning the CMOD assignment. The CYBLE-214009-00 module datasheet shows the internal schematics of the module (not the evaluation board):

Both P4.0 and P4.1 are hardwired inside the module with 2.2 nF (CMOD) and 10 nF (CTANK) capacitors. It is true that they are not broken out on the module pads or the evaluation board pins, but the assignment within PSoC Creator is correct. This screenshot is from the PSoC_4_BLE_CapSense_Slider_LED example project, which I opened in PSoC Creator 4.0 and then changed the target to the CYBLE-214009-00 module--note the top row with CMOD assignment to P4[0]:

This project compiles without error.

user_1377889's picture
User
9572 posts

@jrow

How it comes that the project that Brian supplied does not compile? When setting the Cmod pin to "auto assign.." the fitter chooses P3_2 as Cmod pin, setting to P4_0 is not accepted and flagged as error.

 

Bob

IrY100Fan's picture
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5 posts

Building on what jrow said...

It seems that the CapSense CSD component will auto-assign the CMod signal to pin P4[0], but the CapSense component will not compile.  This also holds true with the example files in PSoC Creator 4.  The CapSense CSD examples work, the CapSense ones do not.

-Brian

IrY100Fan's picture
User
5 posts

Continuing this conversation (if I may)...

Is the newer CapSense (v3.10) component supposed to work with the CYBLE-214009-00 module?

Are there any appreciable differences in performance between the CapSense (v3.10) and CapSense CSD (v2.50) components?
(I see the API's are different so it looks like I'll have to do some backtracking and code corrections if I need to use the CapSense CSD component.)

-Brian

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