BLE stack optimization in CY4247 | Cypress Semiconductor
BLE stack optimization in CY4247
I need to add a good amount of code but the BLE stack is occupying almost 69% of flash and SRAM use is nearing 98%. For SRAM, I found http://www.cypress.com/blog/psoc-creator-news-and-information/controllin.... But I am still looking for BLE flash reduction. Does any way exists? Thanks in advance.