This in under creater 3.2. Using the ADC appear to limit the entire of port 1 to slew rate fast . Why ?
Welcome in the forum, Dominic.
ADC uses the analog part of the GPIO-pins, so there the slew-rate is not relevant. Can you specify a bit deeper what you want to have changed?
Very helpful could be a project showing the error. Can you post your complete project, so that we all can have a look at all of your settings? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
The ADC component appears to require Port1 to have a slew rate of fast if the Vref is by passed. I think this is a bug.
I'm using Pioneer board and CY8C4245AXI-483 and I cannot set Vref bypassed without error. Please upload project to check.
Now I can see and reproduce your issue. Seems you're right, that should not be. I would suggest you to create a MyCase: at top of this page "Support & Community -> Technical Support - Create a MyCase" and attach the example project with a bit of description.
I have a case open but I'm not sure the person understands the analogue signal shouldn't affect the slew rate .
When you attached your project someone will recreate the issue.