Using datapath as 'latch' possible? | Cypress Semiconductor
Using datapath as 'latch' possible?
I'm currently evaluating the datapath parallel in/out capabilities. So, I decided to make a latch (like D-FF). This latch has one 8-bit input, two 8-bit outputs, one clock (strobe) input and one SEL input for selecting the 8-bit output.
I configured the datapath with PI_SEL = PIN to force the SRCA to be always parallel input. There are two configurations where the A0WRSRC/A1WRSRC is the ALU. This means that the parallel in goes in either A0 or A1.
The parallel output is always enabled and depends on SRCA selection (A0 or A1). For my understanding this works even if the SRCA is forced to be the PI, right? So, for the two configurations also A0/A1 are chosen as the SRCA input.
Now, I wonder if this will work when the UDB gets a single clock strobe. I'm not sure if I understand the datapath correctly:
on the rising edge of the strobe input, the parallel input will be written to either A0 or A1 depending on the SEL input. Will this value also immediately be seen on the parallel output or does this need two clock strobes?