Unable to pack the design into 4 UDBs - Control file doesn't help | Cypress Semiconductor
Unable to pack the design into 4 UDBs - Control file doesn't help
My project doesn't fit into the UDBs. The workaround with the control file doesn't work as mentioned. Any idea?
The placer is not able to place all of the carry chains without backtracking. It fills one UDB bank to 15/16 and the other to 7/8 and cannot place the final 2-datapath chain. As a workaround, add a control file to the TopDesign component (in Workspace Explorer's Components tab) with the following lines: ATTRIBUTE placement_force OF \Timer_ADPActiveTime:TimerUDB:sT16:timerdp:u0\ : LABEL IS "U(2,0)"; ATTRIBUTE placement_force OF \Timer_OutputPeriod:TimerUDB:sT24:timerdp:u0\ : LABEL IS "U(3,1)"; ATTRIBUTE placement_force OF \Timer_OutputActiveTime:TimerUDB:sT24:timerdp:u0\ : LABEL IS "U(0,1)"; This will fill the datapaths in the second UDB bank and allow the placer to assign the remaining datapaths.