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Unable to pack the design into 4 UDBs - Control file doesn't help | Cypress Semiconductor

Unable to pack the design into 4 UDBs - Control file doesn't help

Summary: 17 Replies, Latest post by Bob Marlowe on 14 Oct 2016 12:30 AM PDT
Verified Answers: 0
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EyA
user_180295388's picture
User
13 posts

My project doesn't fit into the UDBs. The workaround with the control file doesn't work as mentioned. Any idea?

The placer is not able to place all of the carry chains without backtracking. It fills one UDB bank to 15/16 and the other to 7/8 and cannot place the final 2-datapath chain. As a workaround, add a control file to the TopDesign component (in Workspace Explorer's Components tab) with the following lines: ATTRIBUTE placement_force OF \Timer_ADPActiveTime:TimerUDB:sT16:timerdp:u0\ : LABEL IS "U(2,0)"; ATTRIBUTE placement_force OF \Timer_OutputPeriod:TimerUDB:sT24:timerdp:u0\ : LABEL IS "U(3,1)"; ATTRIBUTE placement_force OF \Timer_OutputActiveTime:TimerUDB:sT24:timerdp:u0\ : LABEL IS "U(0,1)"; This will fill the datapaths in the second UDB bank and allow the placer to assign the remaining datapaths.

bhwj's picture
Cypress Employee
33 posts

Hi EyA,

Where you able to resolve this ?Seems to me like the issue is because of too many P-terms ,tried removing few pterms (Mux logic)it was able to place and route successfuly ,If you still see this issue, please create a technical support case .Cypress.com-->Support-->Technicalsupport.

 

 

EyA
user_180295388's picture
User
13 posts

Hi!

Thanks for the feedback. I didn't try to go on in that direction but changed to a different approach. What bothered me is the message of Creator. It didn't point in the right direction. Maybe, optimization is possible.

user_14586677's picture
User
7645 posts

In PSOC Creator 3.3 there is a tab upper right of screen thats shows resources

used and remaining. To keep track of where you stand.

 

Regards, Dana.

Hi,

I now have this "Unable to pack the design into 4 UDBs" problem. I had started with my working UART implementation and added CapSense components, per the CapSense demo. Before adding any of the code, I tried to build, to see if I had broken it (yet). Archive attached. Thanks in advance.

user_1377889's picture
User
9842 posts

Welcome in the forum, Dave!

So use SCB based UART and two TCPWMs configured as PWM. This will use no UDBs at all.

Preserve UDBs as long as possible, they are very valuable!

 

Bob

Cool! Thanks Bob. BTW - What's that in your cat's mouth? :-)

user_1377889's picture
User
9842 posts

Answer: a mouse  ;-)

 

Bob

Hi Bob,

So as a baby-steps approach, I went back to my working UART project and added an SCB UART. I must be missing something obvious. I can step through the code fine, and have had it connected to external hardware. It's as if the pins are not connected to the UART. Bytes sent don't seem to actually hit the tx pin, and the rx pin doesn't seem to see the traffic I've presented to it either.

user_1377889's picture
User
9842 posts

Baby step aproaches do not use interrupts, change your design to interrupt driven at a later stage.

Besides: you are using the same interrupt handler for both your UARTs. That might not work, because the interrupt clearing is different for an SCB based UART.

The component itself already handles a circular buffer, so set the Rx buffer size to 40 as the Tx buffer and remove the interrupt handling.

Use UART_SCB_1_SpiUartGetRxBufferSize() to determine whether there are bytes, retrieve them with UART_SCB_1_SpiuartReadRxData(). That long names are not my fault.

Is there a special reason why you are providing your UARTs with your own clock and not using the internal clock?

And last: Which board are you using? CY8CKIT_0???

 

Bob

Thanks Bob,

I'm using the CY8CKIT_042. I'm using an external clock in order to generate the 31.25Kbaud for MIDI. I had adapted this from an example project, maybe there's a better way? You're right, non-interrupt would be a better baby step. Just so I understand what you mean about the same interrupt handler -- are CY_ISR_PROTO(SCB_1_RxInt); and CY_ISR(SCB_1_RxInt);  somehow connected to CY_ISR_PROTO(MyRxInt); and CY_ISR(MyRxInt)? (I had copied the structure of your original design, but my understanding of it could well be way off).

I'll take another swing without interrupt. Thanks for all your help.

-Dave

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