TCPWM->PWM with switch -> wrong output? | Cypress Semiconductor
TCPWM->PWM with switch -> wrong output?
I configured a TCPWM block as PWM with the following settings:
- input clock 1Hz
- left aligned
- normal PWM mode
- switch input active
- Period 4, period buffer not used/switched
- Compare 1, compare buffer 3
- Compare output connected to switch input
From the above I'd expect a frequency of 0.2Hz (5s), and a pulse width of 1s and 4s. However, I can only see the 1s pulse with a period duration of 5s, so it seems the switch isn't recognized. Cypress confirmed that the OV/UV/CC signals are based on HFCLK, so their pulse widths are one HFCLK cycle in length. Since the TCPWM samples the trigger input with HFCLK the pulse couldn't be recognized by the TCPWM itself.
I added a SRFF with HFCLK as clock, TCPWM compare output as 'set' and TCPWM overflow as 'reset'. Now the TCPWM switches the compare values as expected, but the expected 4s pulse is only 3s. Can anyone reproduce it?