Strange clock behavior | Cypress Semiconductor
Strange clock behavior
I have an external 24MHz crystal and the ECO is using this. In the configure system clocks window, Direct_Sel, PLL1_Sel and PLL0_Sel are all set to use ECO. HFCLK uses Direct_Sel, and the SYSCLK divider is 1. Everything is thus running at 24MHz.
I have 2 clocks placed in my .cysch. One is set to 24MHz the other to 1kHz. On the clock tab in the .cydwr page one has a divider of 1 the other 24,000. This all seems correct.
There is a timer using the slow clock, its count is set to 1000. I have an ISR on the slow clock TC. The ISR toggles an LED. The LED, in operation, flashes at 0.5Hz - which is also correct.
But, if I set IMO to 40MHz but leave everything else the same (still using the 24MHz HFCLK for everything that I can see), then my LED flashes faster thus the 1kHz clock (based on HFCLK) must have sped up. Measuring the LED frequency I can see that the 1kHz clock is actually 40/24 * 1kHz. That is, my slow clock is using IMO.
Why? [Recap: the 1kHz clock has HFCLK defined as its source]