Status register -> read by polling & interrupt | Cypress Semiconductor
Status register -> read by polling & interrupt
I've a question about the status register and the interrupt generation: I use one bit of the SREG for interrupt generation (using sticky/clear-on-read mode). The other bits are used to indicate the status of the component.
So, in order to use the component properly I've to poll the status register prior to writing data to the component. The question is: what happens if the write function checks the status register and the component generates the interrupt condition at the same time? Do I have to implement some special approach to avoid missing interrupts?