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SPI - microwire mode

Summary: 1 Reply, Latest post by Saheem on 12 Nov 2014 09:27 PM PST
Verified Answers: 0
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Yev's picture
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 Hi all,

I am trying to control this chip (93C66) with the following settings:

ORG at Vcc: 16bit registers

Commands: 11bits

Data: 16bits

First, I tried used SCB with SPI microwire mode.  That, by default, has SS active LOW, whereas I need CS active HIGH.  So, imiplemented the CS with firmware.  Reading the chip was not a problem, but writing to it does not work.  Microwire protocol within the SCB implies alternation between WRITE to the chip READ from the chip procedures.  So, if I need to READ a memory address, I do the following:

static uint16 spiReadAddx(uint8 addx)


    /* Set the chip select active (HIGH in the case). */


    /* Clear the RX buffer. */


    /* Send the address with START bit and OPCODE. */

    SPI_SpiUartWriteTxData(READ_OPCODE_MASK | addx);

    /* Wait until you get something back. */

    while (SPI_SpiUartGetRxBufferSize() == 0){/*Do nothing. */

    /* Reset the chip select line. */


    /* Return the result. */

    return (uint16)SPI_SpiUartReadRxData();


But in the case of WRITE to a memory, I need to send two packets (not counting WRITE ENABLE command):

    /* Send the address with START bit and OPCODE. */

    SPI_SpiUartWriteTxData(WRITE_OPCODE_MASK | addx);

    /* Send the data. */


The problem is that SCB sends the first packet (WRITE command), waits for a response (SCLK active, MOSI high), sends the second packet (DATA), waits for the response (SCLK active, MOSI high).  After sending the first packet, it puts the chip into write mode and by toggling SCLK and keeping MOSI high, it records a from value (0xFFFF).  What I need instead is:

send first packet (WRITE cmd), send second packet (DATA), wait for response (this is not necessary)

Does anyone have any suggestions how to fix it?

Thank you.

Saheem's picture
Cypress Employee
18 posts


I believe you are referring to the National Semiconductor MicroWire mode in SPI SCB of PSoC 4.

I referred to the details on this mode from:

This mode is a half duplex communication and hence there is alternate write and read. After the transmission of 1 byte, the SCB waits for a response from the EEPROM and then transmits the next byte.

Also, this is how the EEPROM (93C66) is designed to work as I read from the datasheet:

Please note that in Page 7 of the above datasheet, under the "Write" section, it is mentioned that "After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN". Please confirm you are doing this.

Also note that the CS specifications are different for Read and Write operations. Make sure you follow the timings as mentioned in the 93C66 datasheet

Update us on your progress with this project.





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