Question about PSoC 4 architecture | Cypress Semiconductor
Question about PSoC 4 architecture
I'm working on an assignment for my studies, I'm making a system that measures the voltages of two incoming channels with the SAR ADC component. I understand that this component resides within the Programmable Analog block of the PSoC 4. Another part of the application writes the measured voltage of the first channel to a 7-segment display, which is located on an extension board. The display has four digits, only one digit is written to the display at a time, but with a high enough refresh rate the user won't notice any flickering.
The frequency I chose for writing a digit to the display is 200Hz. I have implemented this with a Timer Counter, where the clock frequency is 100kHz and when the counter hits the 500, an interrupt is generated (writing the digit).
This was fine when (at first) I only had 1 Analog channel to measure. But with 2 analog channels the PSoC appeared to have trouble reaching the 200Hz (this I assume as I clearly saw flickering). I think I have solved the problem by reconfiguring the SAR ADC with a higher sample frequency (now at 12Mhz) and a lower averaged result (from 256 to 64 samples), which leads to a result within 117us per channel. I can't see the 7-segment display flicker any more:)
But wait, why would the ADC influence my 7-seg display in the first place? This I don't understand, I was hoping that someone can shed some light here. I thought the ADC is implemented in the (programmable) 'hardware', so it won't take up any resources from the ARM microcontroller, right? Also the Timer Counter resides in 'hardware' yes? (in the programmable digital block?)
If more info (or the project files?) is needed for giving an answer, let me know!