You are here

Quantitative capsense | Cypress Semiconductor

Quantitative capsense

Summary: 3 Replies, Latest post by jonpry_1596711 on 03 Jun 2016 10:55 PM PDT
Verified Answers: 0
Last post
Log in to post new comments.
jonpry_1596711's picture
5 posts


    In my application we are attempting to perform quantitative capacitance measurements using the CY8C4247. I realize that this is not an application the chip was designed for and we likely will have to do our own qualification. There are a couple of major problems we are having. The following the the model we use to convert the raw counts into capacitance. It is derived from your capsense design guide. (mdac,cdac,sdiv) are parameters used for the capsense component. We are using PRS-12 to improve linearity. 

def toPf(count, mdac,cdac,sdiv, t=0,cc=0,cm=0,cadc=0):
   uaperbit = 1.2 * 1e-6; #1.2ua per bit

   cdac = mdac * (uaperbit + t*cm); 
   mdac = cdac * (uaperbit + t*cc); 

   cmax = ((1<<16)-1)
   vref = 1.2 + t * cv
   fsw = 48000000.0 / (2 * sdiv) / 2; # by 2 for PRS!!!!

   count += cadc*t

   count = max(0,min(cmax,count))
   cs = (count * mdac) / (cmax * vref * fsw) + cdac / (vref * fsw)

   return cs * 1e9


The first question is, why does changing cdac/mdac result in a change in the measured capacitance value? This does not really make sense from the model. 

Secondly, we are attempting to fit this model to observed data over a temperature range in order to derive the thermal coefficients. However it does not fit well. I suspect that our model is not good enough. Is there another theoretical model of capsense operation? This one does not include any term for the external Cmod capacitance which should have some effect on the measured value. Also we are using shield and I'm guessing that varying shield drive may cause issues. 

Lastly, now that SP2 is out, CSX is an option for us. Is there any information available on CSX temperature effects? I could not even find a way to convert CSX measurements into capacitance values. 

Any advice would be much appreciated. 




Jon Pry

Ramesh B's picture
Cypress Employee
36 posts


Can you please attach the project here. We would like to debug the project. Please attach the project here.


Ramesh B

jonpry_1596711's picture
5 posts

The project is cluttered with a lot of code specific to our hardware. I could create a simplified version but the reality is that we are not doing anything more than using CSD with PRS12 and fixed IDAC settings to measure a fixed capacitance. We also measure the temperature and then send the sensor raw values to a PC to analyze using some python code. The actual process is quite convoluted as it involves BLE, a phone, and a webservice. I can provide JSON formatted data dumps of the measurement of several fixed capacitances over varying temperature. I feel this would actually be much more helpful than the firmware code itself. 

I did figure out that we were using IMO to run sysclk during capsense and switching this to ECO has reduced the temperature drift by an order of magnitude. However, we need at least another order of magnitude in performance. My plan right now is to measure a reference capacitance with a variety of modulation idac values with compensation idac off. Theory being that we can calculate the true microamps/bit of the modulation IDAC at current operating conditions because this value is whatever causes the measured capacitance to be nearest constant.  The only problem is that I have not yet come up with a way to directly measure Vref drift or any of the SAR adc gain/offset parameters. Without these it seems the mdac calibration may not work correctly. 



jonpry_1596711's picture
5 posts

While there seems to still be a bajillion factors I can't quite control. I did manage to get down to about 1 femtofarad/C of drift. The single largest source of error was actually the equations in cypress documentation being wrong. I went through the trouble of building a spice model of the CSD module to verify this and derived the count to capacitance formula. In case anyone is interested, you eventually end up with some variation of:


   d = (vref * fsw)
   s = count / float(cmax)
   cs = (s * mdac + cdac/2) / d

The key here is the divide by 2. This is not included in cypress documentation. 


Log in to post new comments.