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PSoC 4200L PWM issue | Cypress Semiconductor

PSoC 4200L PWM issue

Summary: 5 Replies, Latest post by Bob Marlowe on 15 Sep 2016 12:09 PM PDT
Verified Answers: 2
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user_466193552's picture
User
12 posts

Hello,

I am having an issue with using the UDB PWM component with 48 MHz HFCLK clocking. Since I was using the USB component, I must set the HFCLK to 48 MHz. When building the project, this warning message apperars:

 

Warning-1366: Setup time violation found in a path from clock ( clk1m ) to clock ( clkphase ).

 

And it indicates the max frequency being only 29.8 MHz.

Thanks for your help!

 

I have attached the project to this post.

user_1377889's picture
User
10708 posts

The trigger input of the PWM was not connected. After connection with an input GPIO set to double sync the project compiled error-free.

There are some components not on latest revision. Consider updating (Creator v3.3 CP3 -> Project -> Update Components)

 

Bob

user_466193552's picture
User
12 posts

Ah, I'm sorry! I forgot the project contained two different files. It was the "pcbtesttablet1" project that required attention, which does have the trigger pin connected. The "design01" project was created by mistake. Thanks!

user_1377889's picture
User
10708 posts

Apart from your self-made warnings and errors ;-)

Set trsignal input to "Double Sync".

 

Bob

user_466193552's picture
User
12 posts

That worked!! I can't believe it's such a simple setting that I overlooked. Spent 4 hours trying to find it, and I feel so dumb.

 

   ヘ⌒ヽフ
( ・ω・) Thanks Bob~~
/ ~つと) 
 

user_1377889's picture
User
10708 posts

Congratulations!

and...

You're always welcome!

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