PSoC 4 GPIO toggle speed | Cypress Semiconductor
PSoC 4 GPIO toggle speed
I'm writing data to an 8-bit parallel bus, latched with a WR strobe, and I've noticed that the fastest rate at which I can strobe the GPIO pin attached to the WR signal is 167ns, or 8 clock cycles.
The code is optimized down to a pair of STORE instructions, one to clear the GPIO bit and one to set it again:
0x0000027C ldr r3, [pc, #8] ; (288 <toggle_test+0xc>)
0x0000027E movs r1, #0
0x00000280 movs r2, #1
0x00000282 str r1, [r3, #0] ; WR low
0x00000284 str r2, [r3, #0] ; WR high again
0x00000286 b.n 282 <toggle_test+0x6>
0x00000288 .word 0x40040100
According to the Cortex-M0 instruction set, each store should take 2 cycles, and the branch should take 3. However, I measure the stores as actually taking 8 cycles, and I'm trying to understand why.
My first thought was that running out of flash memory was slowing things down, but I modified the code to run from RAM and get the same 8 cycle pulse. I've looked at the data sheet and the TRM and haven't found any other information that explains this timing.
Does anyone know the reason for this? Is there any way to speed it up?
48 MHz clock (internal)