Its out -
Nice factoid in the PSOC 4 -
The PSoC 4100/4200 includes a hardware multiplier that
provides a 32-bit result in one cycle.
Maybe this will go a long way to FIR and IIR w/o DFB, although latter clearly
This is not too shabby -
SARSEQ is a dedicated sequencer controller that automatically sequences the input mux from one channel to the next
while placing the result in an array of registers, one per
■ Control SARMUX analog routing automatically without
■ Control SAR ADC core (such as resolution, acquisition
time, and reference)
■ Receive data from SAR ADC and pre-process (average,
■ Results are double-buffered so the CPU can safely read
the results of the last scan while the next scan is in progress.
The features of SARSEQ are:
■ Eight channels can be individually enabled as an automatic scan without CPU intervention
■ A ninth channel (injection channel) for infrequent signal
to insert in an automatic scan
■ Per channel selectable
❐ Input from external pin or internal signal (AMUXBUS/
❐ Up to four programmable acquisition time
❐ Default 12-bit resolution, selectable alternate resolution: either 8-bit or 10-bit
❐ Single-ended or differential mode
❐ Result averaging
I checked one hour before (it was linked from the AppNote), and it wasn't there yet :(
I thought the SARMUX is like the already existing component on the 5LP, but it seems much more capable. Looks really nice. Unfortunately, without DMA the high sample rate cannot really be used.
The PSoC5 already has hardware multiple (even divide) since its standard on the Cortex-M3 (see http://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M3 or http://www.arm.com/products/processors/cortex-m/cortex-m3.php?tab=Specif... )
EZI2C seems to be in hardware now too. The whole communication interface stuff is in hardware now - this will really free up resources when they are used.
The multiplier on a $ 1 part is what is significant.
I saw this in TRM, DMA, maybe the families with expanded FLASH and UDBs will
have DMA, or is this just a cut and paste from PSOC 3/5....
PLD Macrocell Read-Only Registers
The outputs of the eight macrocells in the two PLDs can be accessed by the CPU/DMA as an 8-bit read-only register. Macro
cells across multiple UDBs can be accessed as 16 or 32-bit read-only registers. See UDB Addressing on page 160.
The mentioning of DMA seems to be a copy-paste error. It is nowhere else specified - and it should have its own section in the TRM when it would exist.
The ARM site on M0 and M0+ distinctly absent any discussion of DMA.
4100 vs 4200 differences seem to be UDB not in 4100, core speed -