Project Not Compiling with Two SCB components | Cypress Semiconductor
Project Not Compiling with Two SCB components
I am using PSoC4100M for a project. I have two SCB components. One configured as I2C master and the other as UART. The I2C and UART pins are routed to different ports. I2C on port 1 and UART on port4.
When I compile the project I get CyDsFit Error which says
"E2809: Unable to find a valid placement for pins and fixed-function blocks. See the Digital Placement's Detailed placement messages section in the report file for details"
and gives the following suggestion
The placer is not able to place all of the carry chains without backtracking. It fills one UDB bank to 15/16 and the other to 7/8 and cannot place the final 2-datapath chain. As a workaround, add a control file to the TopDesign component (in Workspace Explorer's Components tab) with the following lines: ATTRIBUTE placement_force OF \Timer_ADPActiveTime:TimerUDB:sT16:timerdp:u0\ : LABEL IS "U(2,0)"; ATTRIBUTE placement_force OF \Timer_OutputPeriod:TimerUDB:sT24:timerdp:u0\ : LABEL IS "U(3,1)"; ATTRIBUTE placement_force OF \Timer_OutputActiveTime:TimerUDB:sT24:timerdp:u0\ : LABEL IS "U(0,1)"; This will fill the datapaths in the second UDB bank and allow the placer to assign the remaining datapaths.
I added the above lines to the control file. But it still gives the same error.
Please find attached the project bundle.