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Problem with I/O as ext. timer's clock | Cypress Semiconductor

Problem with I/O as ext. timer's clock

Summary: 15 Replies, Latest post by danaaknight on 02 Aug 2013 06:54 AM PDT
Verified Answers: 0
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ftoffolon's picture
15 posts

Hi everybody,

in my psoc4 proj. template with PSOC 4 pioneer kit I'm trying to test the capability of get a external time base tick for RTC purpose, getting it from mains power zero cross (50 Hz, e.g.).

To scale it into seconds tick, I've routed the I/O with ext. freq. to a clock with design-wide clock editor :

.cydwr tab -> add design-wide clock -> clock type existing -> source pin -> select pin -> I/O pin.

and the new clock signal routed into a timer counter block, with a period equal the ext. freq. (e.g. 50), enabling the overflow interrupt, so I expect that interrupt comes every second (time for 50 pulses with 50 Hz is 1 second).

This approach doesn't works.

With some debug I/Os I've done some test :

- with a dig. output pin connected to Timer's overflow pin  and a toggle I/O driven by Timer isr I've checked a ~ 5kHz freq. (not 1 Hz, as I expecetd).

- if I check through a flip-flop the freq. of clock generated by ext. I/O, this is 50 Hz.

- if I use an int. clock with 50 Hz freq. instead the ext. 50 Hz, Timer's OV interrupt is right and drives an isr every second.

There is someone with an idea where I was wrong or with any suggestion ?


Thanks in advance.



Are someone with an idea where I woas wrong ?



user_1377889's picture
9301 posts

Have a look into Brad's suggestions how to configure pins for clock-signals




user_119377051's picture
866 posts

Hi ftoffolon,
I/O pin and interruption these have many setting points.
Input mode, Transparency, Buffer mode or Selection of edge...etc.
You rather upload your project as bundle that is good.
When you do that you can get more helpful advices.

user_14586677's picture
7646 posts

The input clock has extrmely slow rise/fall times, read input spends excessive

time at threshold region of input buffer = potential to oscillate. And that would

be aggravated by noise on top of input being at threshold. That could account

for your seeing a much higher Timer OV, eg it would be clocked at a rate >>

50 Hz.


1) How did you signal condition line Vin to pin ?

2) Consider using a comparator with Hysteresis as conditioning for Vinac.


Regards, Dana.


user_460349's picture
1362 posts

 If you only need the AC signal for clock input source, you don't need zero crossing, Just use a compartor with hysteris to get a 50hz pulse, set the compare level away from 0V. you will not get 50% duty cycle, but as a clock source, it doesn't matter.

user_119377051's picture
866 posts

50Hz is
relatively slow. It's a LANT signal that has slow rising and slow falling.

Signal conditioning is important. as dana say.

Let me show
you one example of external circuit.

precautions is voltage at input pin needs to clamping.

If this
value excess Vdd and Vss, psoc is going to restart or break down.

Signal Conditioning [click
to enlarge]


ftoffolon's picture
15 posts

Thanks all for quick replys,

actually I simulate mains freq. using a function generator that drives a square waveform (0 - 5Vdc, 50Hz), so now I don't mind over/under voltage consideration (now I'm still work with pioneer kit).

As suggest into psocsensei forum (thanks Bob 4 link), I've tried to route the clock generated through zero cross input as direct as possible to another output pin for check freq and it's good, but still problems on count. It's seem timer (fixed function one, because my target is cy8c41xx, so without UDB) runs with another clock, with ~50*5kHz freq.

Pin that reads zero cross signal is configured as dig. input with hi imped., input buff. enabled and trasparent mode for synch (others kind of sync. has no effect).

Extract from an example schema from another product with uC (PIC16/18) with internal clamp diodes, that I can plan to use

for zero cross signal conditioning :

*230 Vac - 50Hz into R3

*zero cross to PSoC, eventually with external clamp diodes (if there're no internals or there're current problems, I'll check datasheet better).

In that example there's no hyst. comp because the realted uC that use it has schmitt trig. for each I/O. I'll plan to check if hyst. comp. is required for this clock input.





user_14586677's picture
7646 posts

Max pin injection current is -


user_119377051's picture
866 posts

You are using a
function generater for the input signal.

But didn't work.

I doubt to comparator
of PSoC4,

that is FF module not
UDB module that has no intenal reference voltage.

And also PSoC4 seems
has no analog reference module.


Therefore, you owe to
give it by external reference voltage via analog pin.

It might be 1V to
2.5V is well.

Add this to negative
input of comparator.


Another worry.

Input clamp circuit
is still need.

Take look this


Your Circuit [click to


Ideal Circuit [click to



ftoffolon's picture
15 posts

Thanks dana & PSoC73,

you're right about use external clamp diodes for limit injection current for PSoC4 applications.

I've done more test : always with clock generated by ext. pin (50Hz from ext. freq. gen., a square wave, 5-0Vdc) that drives FF timercounter that I want to use for 1 second period tick isr, if I disconnect ext. clock from pin, timer still runs and generate ovr isr, always with a ov interrupt period with a freq ~ 5kHz.

Other test : if I drive timercounter with 50Hz derived by HFCLK (I'ev checked it into clocks tab of cydwr file), it works good and generare interrupt every seconds. Instead if I get this 50Hz internally generated and put into a toggle flip flop (e.g.) and route the filp flop Q out to a new design-wide clock and route this new one to the timercounter, same behavior than I/O driven clock.

It seems to me that clocks built from design-wide isn't good for fix funct. timercounter. From timercounter datasheet I've read this into Clock Selection paragraph:

"The clock is provided using the clock terminal. This clock must be from the global clock
generation logic. Clock prescaler functionality is available within the TCPWM component. "

Does "global clock generation logic" means clock that cames only from internal clocks (through divider) ?


user_14586677's picture
7646 posts

Not my place to ask, but consider filing a tech case at -






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“Technical Support”

“Create a Case”


and let forum know result.


Just give them the link to this thread as basis of CASE.


Regards, Dana.

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