Problem with I/O as ext. timer's clock | Cypress Semiconductor
Problem with I/O as ext. timer's clock
in my psoc4 proj. template with PSOC 4 pioneer kit I'm trying to test the capability of get a external time base tick for RTC purpose, getting it from mains power zero cross (50 Hz, e.g.).
To scale it into seconds tick, I've routed the I/O with ext. freq. to a clock with design-wide clock editor :
.cydwr tab -> add design-wide clock -> clock type existing -> source pin -> select pin -> I/O pin.
and the new clock signal routed into a timer counter block, with a period equal the ext. freq. (e.g. 50), enabling the overflow interrupt, so I expect that interrupt comes every second (time for 50 pulses with 50 Hz is 1 second).
This approach doesn't works.
With some debug I/Os I've done some test :
- with a dig. output pin connected to Timer's overflow pin and a toggle I/O driven by Timer isr I've checked a ~ 5kHz freq. (not 1 Hz, as I expecetd).
- if I check through a flip-flop the freq. of clock generated by ext. I/O, this is 50 Hz.
- if I use an int. clock with 50 Hz freq. instead the ext. 50 Hz, Timer's OV interrupt is right and drives an isr every second.
There is someone with an idea where I was wrong or with any suggestion ?
Thanks in advance.
Are someone with an idea where I woas wrong ?