Port 3.x not usable as output if CapSense enabled? | Cypress Semiconductor
Port 3.x not usable as output if CapSense enabled?
I'm struggling into the next pitfall while 'exploring' PSoC 4 ;)
I'm using a Pioneer kit and want to output a signal on port 3.6. The CapSense part (5-pole slider on port 1.1-1.5) is also enabled, which means that P4.2 is used as Cmod.
Now, PSoC Creator tells me that port 3.6 cannot be used when P4.2 is configured as Cmod (error: pl.M0046:E2725 P3 cannot be used as an output when P4 is used as Cmod).
I've gone through datasheet and reference manual, but I couldn't locate anything indicating that port 3 has reduced capabilities if CapSense is enabled.
So, I'm getting a bit frustrated because I've to fight with UDB & Verilog and maybe incomplete datasheets/reference manuals or a faulty implementation in PSoC Creator - but where's the error?
I connected Cmod to P4.1 to 'test' it (P4.2 is fixed function for Cmod) - interestingly, in this case Creator only throws a warning that automatic rerouting has been done, but it compiles successful.