PI -> A0, load a byte | Cypress Semiconductor
PI -> A0, load a byte
setup: datapath have it's static configured parallel input on D0..7 bus. we want to load a byte into A0 accumulator on rising edge of routed input. if we connect routed input to clk in of datapath, will we have a byte loaded immediatly after rising edge of CLK? I'm receiving garbage. or there is some registered logic inside and we must give a whole pulse (what polarity?) on CLK, with both rising and falling edges? or it takes 2 cycles - one for PASS alu operation, one for A0 writing? it's unclear.