Interface PSoC 4 to 8-bit uP bus | Cypress Semiconductor
Interface PSoC 4 to 8-bit uP bus
I'm brnad new to PSoC development and have been experimenting with ways to perhaps interface the PSoC 4 with a low-speed 8-bit uP bus for both read and write. This would allow the PSoC to work like a memory-mapped I/O device on the uP's bus. My main concern right now is it seems like, even running at 48 MHz, interrupt processing would be too slow to keep up with the timing of a 1 or 2 MHz bus. If I use an interrupt caused by my target address range appearing on the bus, I don't think it is possible to sample the address, read the correct data from memory, and make it available on the data bus via GPIO pins within the 500ns of a 1MHz clock pulse. In fact, the documentation indicates it takes at least 333ns just to start execution of my ISR. Am I correct to be worried about using interrupts? Should I be thinking about DMA instead? Can this maybe be done esaily some other way, or does it require building my own custom component(s) in Verilog? Has anyone seen or done something similar with these timing constraints?
Thanks much. It's a fascinating platform, and I'm excited to get a firmer grasp on what sort of things are possible.