implementation clarification clock system: external clock / IMO multiplexer | Cypress Semiconductor
implementation clarification clock system: external clock / IMO multiplexer
looking at the PSoC4 technical reference manual and specifically the clocking system, I still worry about the
simple multiplexer muxing IMO and external provided clock signal. Is it always safe, or can there be 'shorter-than-alowed' pulses when switching between these two asynchonous clocks...
... or is the diagram a bit too simple and not showing the real implementation. If so what is the worst case 'hickup' (time delay) when switching from internal (low frequency IMO eg 2MHz) and external provided max clock frequency?
the question i simply seek: it is guarenteed that switching will not make the device go 'bad' due to too short (to high frequency) pulse?