I'm missing something when it comes to setting pins | Cypress Semiconductor
I'm missing something when it comes to setting pins
Ok so I'm on the CY8CKIT-042 pioneer kit.
I have 5 output pins in the schematic set to Port0[4..0], and I have a Control Reg(toCpldController) connected to the pins. The http://www.cypress.com/?docID=49248 document shows that I shouldn't need it, but if I don't have it the project won't build.
They are set to strong drive, as the pin is connected to an input pin on a CPLD.
Trying to control the pins in software like this
Gives me a nice up then down pulse that is about 780~800ns long.
If I do
I get a pulse for 20ns which seems impossibly short for a 48mhz cpu especially given a nop op, but then it holds low for 5~8us then start to glitch, as if it is floating. With the Controller methods above I don't see that happen.
What am I missing?