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Fractional Clock Dividers with PSoC 4 | Cypress Semiconductor

Fractional Clock Dividers with PSoC 4

Summary: 3 Replies, Latest post by dhar on 28 Jun 2013 03:47 AM PDT
Verified Answers: 2
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user_460349's picture
1362 posts

A very interesting feature for PSOC4, just wondering what application could be used beside the UART that's being mentioned.


dvorakvik's picture
109 posts

 Hi, all

Perfect solution for USART external clock when using "round" external oscillators e. g. TCXO 40.000000 MHz. 

For PSoC4 clock 40 MHz, oversampling 12 and 115200 Baudrate the fractional divider is 20 + 30/32 = 1.382 MHz



user_51135297's picture
26 posts

Hello. Thanks for this post, I look the link from sensei and it was an excellent explanation about the fractional resources. another interesting topic is

best regards,

dhar's picture
Cypress Employee
8 posts

Another thing to be noted here.The fractional divider is restricted only to digital clocks and not applicable to analog clocks(like ACLK of SAR ADC).

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