FIFO management in verilog | Cypress Semiconductor
FIFO management in verilog
I'm working on my first complex component including datapath and verilog portions. The component exceeds the maximum datapath output number of six outputs, so I decided to make the FIFO management in the verilog part of the component.
This means that the four byte hardware FIFO should be used, but the block and/or status signals should be managed by the verilog part. For this approach I thought about the following:
I configured a bit of the control register for pulsed mode. After writing a byte to the FIFO, the bit of the control register is set. The verilog state machine has four states, from which one state reads the FIFO. The control bit is checked on each state. If the state is not the FIFO reading state, the FIFO byte counter is incremented. If the state is the FIFO reading state, a registered signal is set to save the control bit for the other states. This is done to avoid incrementing and decrementing the byte counter at the same cycle. Can this work?
What I also want to implement is a interrupt signal for the FIFO space left. This means a interrupt pulse generated when there's enough space for 1-4 bytes depending on a component parameter. Now, I'm confused about how to implement it: the byte counter is decremented in the FIFO reading state of the state machine. How can I compare the decremented counter against the threshold in the FIFO reading state?