EZSPI? | Cypress Semiconductor
I was going through the PSoC4 TRM and tripped over "EZSPI" mode. This seems to be an excellent fit for an SPI slave I've been putting together, the main feature being that the SCB hardware takes care of the tight bus timing requirements.
TRM sec. 22.214.171.124 claims that PSoC Creator can do the SCB auto-config for EZSPI, but it doesn't appear to (at least there's no EZSPI checkbox). That section also describes how to do the config by hand, but I think there are some pieces missing, notably how to read/write the "virtual register space" presented over the bus, and how to tell that the contents have changed. The API mentions a user (RAM) buffer for the virtual registers, but I don't see anything in the TRM [Registers] to tell the SCB about it.
I don't mind hacking this in, but I'd like to get some sense that success is possible
Since there appears to be considerable overlap with EZI2C mode (PSoC Creator does have a checkbox for that), I generated one of those and poked through the code it produced. As near as I can tell:
1) There are #define-s for what appear to be the virtual registers (starting at SCB_EZ_DATA), but the TRM [Registers] 16.1.26 only mentions one of the (expected) 32 bytes, with no indication that there might be more. Do these registers actually exist?
2) The generated code appears to do all the virtual register mapping in software, without referring to SCB_EZ_DATA (or its pseudonyms) at all. Similarly, the user (RAM) buffer supplied to the API is only used by software, and isn't supplied to the SCB. This seems to defeat the purpose of EZ mode, i.e. to use the SCB hardware to do all the tight timing.
I'm not typically stymied by implementation/documentation discrepancies, but I'm getting the impression that the EZ feature isn't "all there" yet. Am I missing something obvious? Has anyone seen this feature work?