External clock for TCPWM components - Help please!! | Cypress Semiconductor
External clock for TCPWM components - Help please!!
I have a project using all available UDB - I need two additional frequency dividers to divide external input 'clocks' by a value of 2, or 4, or 8 (with equal M/S output) these values being written to both dividers by the processor.
I am used to doing this sort of thing all the time with PSoC 1 - Wire the PWM clock input to a pin, and all is fine... So just went ahead and developed this project using "dummy" internal clocks to drive the PWMs for testing.
Never read the data sheet carefully enough ;-(
Is there any way out - I cant squeeze more than perhaps a few gates into the UDB's - but have all 4 TCPWM blocks unused - I was hoping to use all 4, but desperately need at least two programmable dividers - input "clocks" are too fast to implement the function in the processor (well, if all else fails I will give it a try under ISR, but the jitter would degrade the whole project if it even worked - inputs are assynchronous and could go up to 1MHz - I could probably limit to 500kHz - but it would be a mess!)
The functions in the UDBs cannot be moved to fixed blocks - there are components I have created to implement phase comparison for PLL of external oscillators, and generation of complex audio waveforms..
I hate the idea, but perhaps I will have to add an external dual HC divider and waste 8 precious pins on the PSoC -
Any ideas would be welcome!