Effective Speed Difference | Cypress Semiconductor
Effective Speed Difference
Summary: 3 Replies, Latest post by danaaknight on 21 May 2013 05:06 AM PDT
Verified Answers: 0
20 May 2013 11:56 PM PDT#1
It is stated in the datasheet that "The flash block is designed to deliver 1 wait-state (WS) access time at 48 MHz and with 0 WS access time at 24 MHz". So, what is really the MIPS difference between 24MHz and 48MHz?