"Divided clock cannot be used with UDB components" error | Cypress Semiconductor
"Divided clock cannot be used with UDB components" error
I am getting the following error when trying to program my device.
Divided clock "ADC_intClock" cannot be used with UDB components, analog components, or pins because its frequency exceeds half of the HFCLK frequency. (App=cydsfit)
I'm unsure how to make sense of this error- I've attached my project for your reference. Any advice is greatly appreciated!