Do the IO pins on PSOC 4200M devices have ESD clamp diodes? Where can I find information on IO pins in the M series devices?
Generally the characteristics of GPIO pins are the same for all members of the PSoC family. So use the pins datasheet, AC/DC electrical characteristics.
Thanks for the reply.
I managed to get the detailed architecture of the IO cell from the System Architecture TRM. It appears that the IO pins do have clamp diodes, except for the over voltage tolerant pins.
One thing that is still unclear is the difference between logic level driving strength and pin level driving strength of IO pins.
Logic level capability is 4mA source and 8mA sink. However the pin capability is 25mA source and 25mA sink.
What is the difference between the two?
"Logic level capability is 4mA source and 8mA sink." When these values are not exceeded the logic level of the pin is still within the tolerance. Some externally connected logic will still see a valid high or low voltage.
"pin capability is 25mA source and 25mA sink." You may use the pin to drive an LED or some other low resistive equipment. The given values may be delivered by the pin, but the output will not confirm to the standard low and high logic levels.
According to datasheet 25 mA is the absolute maximum current supported by GPIO. Usage above the absolute maximum conditions may cause permanent damage to the device. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. So there is no guarantee that specifications mentioned in the datasheet will be met.
Thanks for the reply! Things are clear now :)