Cypress lowers PSOC4 design specs on the fly | Cypress Semiconductor
Cypress lowers PSOC4 design specs on the fly
Has anyone noticed that Cypress has changed the max sample rate of the ADC_SAR_SEQ between version V1.10 and V2.00?
With V1.10 and with AVDD ref, the max sample rate was 1Msps.
With V2.00 and with AVDD ref, the max sample rate has been dropped to 500Ksps, with no way of overriding that limit.
Even the document at http://www.cypress.com/?docID=4830 , dated 26 March, still states the max sample rate is 1Msps. Apparently "The document was not updated correctly to reflect this change.".
This means that none of my designs can be updated.
This is really pissing me off. Cypress just shrugs and less me to redo my designs.
I guess this is the danger of "soft" processors, the manufacturer can retroactively remove features with no thoughts about consequence to the customer.