You are here

Creation of a parallel slave interface (GPIO expander) | Cypress Semiconductor

Creation of a parallel slave interface (GPIO expander)

Summary: 9 Replies, Latest post by danaaknight on 25 Feb 2015 03:53 PM PST
Verified Answers: 0
Last post
Log in to post new comments.
RA1981's picture
User
223 posts

Hi,

 

I want to create a GPIO expander on a PSOC4, but not for a serial interface like SPI/I2C. Instead, I want to interface with a 8-bit data bus. There are many GPIO expander devices for SPI/I2C with several features (even bit-wise input/output functions), but it seems that there are only few to zero devices with parallel interface and extended features (someone might still know the 82C55, for example).

So, I want to create a device with a 8-bit bidirectional data bus, read/write and chip-select strobes as well as some address bits (e.g. for selecting the IO functions and configuring the slave device).

As far as I understand the UDB capabilities, I should use the PI (parallel in) and PO (parallel out) functions of the UDB.

However, I don't get the starting point, e.g. how to synch the I/O operation with the read/write/CS strobes. If someone can help me to build up the parallel interface or pointing into the right direction, this would be great.

Currently I only have some concepts, but they all seem to lead to a 'big' CPU overhead managing the configuration of the ports, which leads to a second problem: if most of the configuration and data transfer to/from the ports to the parallel interface is done by the CPU, I assume that the access timing of the ports will be in a very large area. So, the question is if it's possible to let the UDB do most of the port bit configuration and especially the data transfer.

The questions in short:

1) how to create a parallel slave interface for a 8-bit data bus with read/write/chip-select strobes and address inputs

2) how to keep access timings small

 

Regards,

 

Ralf

user_1377889's picture
User
9572 posts

You could use a verilog based component which you connect to your IO-pins, including the control signals ar R/W, OE and CS. When using the datapath part of the UDB you may use the two fifos for storing and retrieving data. Access is made through component registers for reading and writing, even DMA can be used.

 

Bob

user_14586677's picture
User
7646 posts

What comes to mind is a verilog approach.  Or a simple

combination of port writes and a LUT to create strobes.

 

 

No DMA in PSOC 4.

 

Regards, Dana.

RA1981's picture
User
223 posts

Hi Bob & Dana,

 

thank you for your answer. Currently I'm trying to implement it with simple logic elements (flip-flops, muxer/demuxer, etc.), but I'll have to check it first. (the actual implementation needs 33 macrocells, but the PSoC 4 only have 32 of them). I'll try to optimize...

I'll also look into the verilog and LUT approach, just to see which one needs the lowest ressources, thank you.

 

Regards,

 

Ralf

user_14586677's picture
User
7646 posts

You are always welcome!

 

Dana.

user_14586677's picture
User
7646 posts

The new PSOC 4 M family has DMA !

 

RA1981's picture
User
223 posts

4200M informations are currently rare. Where did you get that overview? I only found the announcement for the new devkit, but no datasheet or user manual.

For my parallel slave interface, it seems that I'm running out of macrocells, so I'll have to think about other implementations. Maybe it would be neccessary to make the way through the CPU :/

It's a pity that the 4200M still has only four UDBs, otherwise I'd consider doing it with the 4200M.

 

Regards,

 

Ralf

user_14586677's picture
User
7646 posts
user_14586677's picture
User
7646 posts

Here is the roadmap -

 

 

user_14586677's picture
User
7646 posts

If you look at this roadmap there are PSOC 4 parts with 8 UDB's,

contact local sales office to get further info, expected release......

 

Regards, Dana.

 

Ignore attachment.....

 

Log in to post new comments.