Confusion regarding parallel in/out configuration of shift register component. | Cypress Semiconductor
Confusion regarding parallel in/out configuration of shift register component.
I should start of by saying it is straightforward to me how to implement the required SR in Verilog-- but I like (even prefer) the DMA access readily provided by the built in component and only am rather a bit confused about the components configuration.
Granted the component allows a bit 'width' to be specified, but both inputs and outputs consist of a single terminal, with no indication that they are (or how to create one). For example if I wanted to do a parallel shift in coming from physical pins 0-7 say, with an 8 bit serial out... How does one go about attaching the eight pins to the input ? Is this possible ? Or am I misunderstanding the design/use case of this component ?